There are two types of commonly used image sensors, Charge Coupled Devices (CCDs) and (CMOS) sensors. Both CCD and CMOS image sensors convert photons into electrons via the interaction of photons with a semiconductor, typically silicon.
CCD sensors transfer charge within the silicon using electric fields and require high charge transfer efficiency (CTE), close to 100%. Consequently, the manufacturing of CCD sensor is tailored to maximize or increase the CTE associated with the device. This involves dopant implantations that result in the substrate being unsuitable for high performance transistor manufacture.
CMOS image sensors do not suffer the CTE issues of CCDs since the charge transfer generally takes place via metal tracks. Typically, the voltage output of a CMOS image sensor is indicative of the intensity of light falling upon it.
As CMOS image sensors are manufactured using either a standard CMOS process or a CMOS process engineered specifically for image sensing, it is common to implement a large amount of imaging signal processing on a sensing device. Typically, an ADC is implemented on the sensing device.
There are three ADC-CMOS sensor architectures that are commonly used in CMOS image sensors: a single ADC per sensing device; a single ADC per pixel column of the sensing device; and a single ADC per pixel of the sensing device. Each of these architectures has relative advantages and disadvantages associated with them that will be appreciated by those skilled in the art.
Referring now to FIGS. 1 to 3, in an embodiment of a column parallel sensor architecture 100, each column 102 comprises pixels 104, an analog comparator 106, and a data storage device 108 which is typically an SRAM. A single digital analog converter (DAC) 110 provides a reference for the comparators of all columns of the architecture. This aids in reducing mismatch between the outputs of each column.
A further DAC 112 receives the input of the reference DAC 110 and outputs an increasing linear voltage ramp 200, 300 in response to a digital input sequence 202, 302. This voltage ramp 200, 300 feeds to both an input of the comparator 106 and to an input of the digital store 108. The other input of the comparator 106 receives an output voltage of the pixel 104 being sampled. When the ramp voltage 200, 300 equals the output voltage 204, 304 of the pixel 104, the comparator output changes from a logic low “0” to a logic high “1”.
The output of the comparator 106 passes to the other input of the digital store 108 where a logic high triggers the digital store 108 to store the digital value received from the DAC 110. This stored value is indicative of the intensity of the light falling upon the pixel 104 being sampled.
FIG. 2 shows ADC conversion with 1 V total ramp voltage and input signal of 400 mV. FIG. 3 shows an ADC conversion with 500 mV total ramp voltage and an input signal of 400 mV. As the number of coding points is the same in both the examples of FIGS. 3 and 4, the gradient of the ramp of FIG. 4 is half that of FIG. 3. Consequently, the point at which the pixel output voltage is equal to that of the comparator occurs later in the cycle, and hence the value stored is increased. This results in differing intensity values.
Referring now to FIG. 6, a linear digital ramp generator 600 comprises a memory device 604, a ramp counter 606 and a digital to analog converter (DAC) 607. In a preferred embodiment the counter 606 is a shift register.
The memory device 604 and the ramp counter 606 receive a clock signal from the same clock (not shown) at their respective clock inputs. Receipt of the clock signal triggers the ramp counter 606 to output a ramp code RAMP currently stored at the ramp counter 606.
Receipt of the clock signal triggers the memory device 604 to output a constant incremental code INC to the ramp counter 606. Upon receipt of the next clock pulse the ramp counter 606 outputs an updated ramp code that is the sum of the previous ramp code and the incremental code RAMP+INC.
Additionally, pixel photon shot noise is the dominant noise mechanism in CMOS image sensors when a pixel is subject to strong illumination as the number of photons detected varies due to the quantized nature of photons. This represents the upper limit of the signal to noise ratio (SNR) of a pixel at strong illuminations.σphoton-shot=√{square root over (Nphotons)}  (Eq. 1)σphoton-shot is the photon shot noise contribution for an electron well with Nphotons electrons.
Strongly illuminated pixels have greater pixel photon shot noise than weakly illuminated ones in a non-linear relationship, such that the effect of photon shot noise is exacerbated at strong levels of illumination. This is shown in FIG. 4.
The resolution of an ADC can be fixed such that sensor performance is not compromised at low illumination levels. Typically, the SNR of weakly illuminated pixels is limited mainly by the quantization noise of the ADC as the contribution of photon shot noise to the total system noise is relatively small in this regime.
As the level of illumination incident upon a pixel increases, this relationship changes and photon shot noise dominates the total system noise. Current sensor arrangements exhibit a read-out rate that is limited by this fixed resolution of the ADC. This is because at higher illumination levels the quantization noise of the ADC is small compared to the photon shot noise.
It is known to use quasi-non-linear voltage ramps such as gamma correction, which is often used to compensate for non-linearity of a cathode ray tube (CRT). Typically, these non-linear ramps are either stored in a look up table or generated using an arithmetic logic unit (ALU).
Look up tables involve storing of a significant amount of data in a read only memory (ROM). The fabrication of a ROM on a device utilizes a significant amount of the device area. This either limits the amount of device area available for sensing applications, or will increase the size of the die with an attendant increase in the cost of the sensor. The fabrication of ROM on the device will increase the complexity of manufacture of the device, with the inherent increased risk of device failure.
Typically, an ALU occupies a significant area of the device area. Additionally, a typical ALU requires a significant amount of current to operate at high speeds.
An approximation to a quadratic voltage ramp can be achieved by subdividing quadratic voltage ramp into linear regions, each having a sequentially decreasing resolution, as shown in FIG. 5. This approach a number of disadvantages associated with it, for example, discontinuities exist at poles associated with the junctions between linear regions. These discontinuities introduce artifacts or distortions in images where the pixel output voltage corresponds closely to the coding value at which the discontinuity occurs.